On the modulo 2n+1 multiplication for diminished-1 operands
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[1] Michael A. Soderstrand,et al. Residue number system arithmetic: modern applications in digital signal processing , 1986 .
[2] Akhilesh Tyagi,et al. A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.
[3] Yutai Ma. A Slimplified Architecture for Modulo (2n + 1) Multiplication , 1998, IEEE Trans. Computers.
[4] Reto Zimmermann,et al. Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).
[5] Haridimos T. Vergos,et al. Fast parallel-prefix modulo 2/sup n/+1 adders , 2004, IEEE Transactions on Computers.
[6] Haridimos T. Vergos,et al. Design of efficient modulo 2n+1 multipliers , 2007, IET Comput. Digit. Tech..
[7] Akhilesh Tyagi,et al. A reduced area scheme for carry-select adders , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[8] Haridimos T. Vergos,et al. Diminished-One Modulo 2n+1 Adder Design , 2002, IEEE Trans. Computers.
[9] Giorgos Dimitrakopoulos,et al. Efficient diminished-1 modulo 2/sup n/ + 1 multipliers , 2005, IEEE Transactions on Computers.
[10] Laurent Imbert,et al. a full RNS implementation of RSA , 2004, IEEE Transactions on Computers.
[11] Haridimos T. Vergos,et al. Modulo 2n±1 Adder Design Using Select-Prefix Blocks , 2003, IEEE Trans. Computers.
[12] Ricardo Chaves,et al. RDSP: a RISC DSP based on residue number system , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..
[13] T VergosHaridimos,et al. Efficient Diminished-1 Modulo 2^n+1 Multipliers , 2005 .
[14] L. Leibowitz. A simplified binary arithmetic for the Fermat number transform , 1976 .
[15] MaYutai. A Simplified Architecture for Modulo (2n + 1) Multiplication , 1998 .
[16] L. Sousa,et al. A universal architecture for designing efficient modulo 2/sup n/+1 multipliers , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[17] Ricardo Chaves,et al. Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures , 2007, IET Comput. Digit. Tech..
[18] Wolfgang Fichtner,et al. A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm , 1994 .
[19] W. C. Miller,et al. An Efficient Tree Architecture for Modulo 2 n + 1 Multiplication Journal of VLSI Signal Processing , 1996 .
[20] P. V. Mohan,et al. Residue Number Systems: Algorithms and Architectures , 2011 .
[21] Haridimos T. Vergos,et al. Handling zero in diminished-one modulo 2 n + 1 adders , 2003 .
[22] Janne Heikkilä,et al. Video filtering with Fermat number theoretic transforms using residue number system , 2006, IEEE Transactions on Circuits and Systems for Video Technology.