Gate leakage current accurate models for nanoscale MOSFET transistors
暂无分享,去创建一个
[1] Paulo Francisco Butzen,et al. Leakage Current in Sub-Micrometer CMOS Gates , 2008 .
[2] Antonio Cerdeira,et al. Gate leakage currents modeling for oxynitride gate dielectric in double gate MOSFETs , 2011, 2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control.
[3] Yong-Bin Kim,et al. Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems , 2010, IEEE Transactions on Instrumentation and Measurement.
[4] R. van Langevelde,et al. Physical Background of MOS Model 11 , 2003 .
[5] Kaushik Roy,et al. Leakage power analysis and reduction: models, estimation and tools , 2005 .
[6] Young-Kwan Park,et al. Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS , 2010, 2010 International Conference on Simulation of Semiconductor Processes and Devices.
[7] Shobha Sharma. Comparative Analysis of Low Power and High Performance PTM Models of CMOS with HiK-Metal Gate Technology at 22 nm , 2012 .
[8] Yutaka Ohno,et al. Electrical properties of the graphitic carbon contacts on carbon nanotube field effect transistors , 2012 .
[9] Yutaka Ohno,et al. Electrical Properties of the Graphitic Carbon Contacts on Carbon Nanotube Field Effect Transistors , 2012 .
[10] Wei Wang,et al. Modeling of Gate Current and Capacitance in Nanoscale-MOS Structures , 2006, IEEE Transactions on Electron Devices.
[11] S. Akashe,et al. Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology , 2013, 2013 7th International Conference on Intelligent Systems and Control (ISCO).
[12] Yong-Bin Kim,et al. A novel technique to minimize standby leakage power in nanoscale CMOS VLSI , 2009, 2009 IEEE Instrumentation and Measurement Technology Conference.
[13] T.A. Fjeldly,et al. Compact Subthreshold Current Modeling of Short-Channel Nanoscale Double-Gate MOSFET , 2009, IEEE Transactions on Electron Devices.
[14] Kaushik Roy,et al. Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.