Scaling analysis of multilevel interconnect temperatures for high-performance ICs

This paper presents a comprehensive thermal scaling analysis of multilevel interconnects in deep nanometer scale CMOS technologies based on technological, structural, and material data from the International Technology Roadmap for Semiconductors. Numerical simulations have been performed using three-dimensional electrothermal finite element methods, combined with accurate calculations of temperature- and size-dependent Cu resistivity and thermal conductivity of low-/spl kappa/ interlayer dielectrics (ILD) based on fully physical models. The simulations also incorporate various scaling factors from fundamental material level to system level: the via-density-dependent effective ILD thermal conductivity, the hierarchically varying root mean square current stress based on SPICE simulations, and the thermal resistance of flip-chip package. It is shown that even after considering densely embedded vias, the interconnect temperature is expected to increase significantly with scaling, due to increasing current density, increasing surface and grain boundary contributions to metal resistivity, and decreasing ILD thermal conductivity.

[1]  M. Shatzkes,et al.  Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces , 1970 .

[2]  L. J. Cox.  Ellipsometry and Polarized Light , 1978 .

[3]  Y.C. Lee,et al.  Internal thermal resistance of a multi-chip packaging design for VLSI-based systems , 1988, 38th Electronics Components Conference 1988., Proceedings..

[4]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[5]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Michael J. Brett,et al.  Three‐dimensional thermal analysis of high density triple‐level interconnection structures in very large scale integrated circuits , 1994 .

[7]  G. B. Kromann,et al.  The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[8]  W. Hunter.  Self-consistent solutions for allowed interconnect current density. II. Application to design guidelines , 1997 .

[9]  Sung-Mo Kang,et al.  iTEM: a temperature-dependent electromigration reliability diagnosis tool , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Chenming Hu,et al.  Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation , 1998 .

[11]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[12]  Alberto L. Sangiovanni-Vincentelli,et al.  On thermal effects in deep sub-micron VLSI interconnects , 1999, DAC '99.

[13]  Yu‐Lin Shen.  Analysis of Joule heating in multilevel interconnects , 1999 .

[14]  Sung-Mo Kang,et al.  Interconnect thermal modeling for accurate simulation of circuittiming and reliability , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[16]  T.-Y. Lee.  An investigation of thermal enhancement on flip chip plastic BGA packages using CFD tool , 2000 .

[17]  P. Wayner,et al.  Thermal conductivity study of porous low-k dielectric materials , 2000 .

[18]  O. Paul,et al.  Process-dependent thin-film thermal conductivities for thermal CMOS MEMS , 2000, Journal of Microelectromechanical Systems.

[19]  E. H. Sondheimer,et al.  The mean free path of electrons in metals , 2001 .

[20]  K. Banerjee,et al.  Global (interconnect) warming , 2001 .

[21]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[22]  Bumpless Build-Up Layer Packaging , 2001, Packaging, Reliability and Manufacturing Issues Associated With Electronic and Photonic Products.

[23]  K. Saraswat,et al.  Analytical thermal model for multilevel VLSI interconnects incorporating via effect , 2002, IEEE Electron Device Letters.

[24]  W. Steinhögl,et al.  Size-dependent resistivity of metallic wires in the mesoscopic range , 2002 .

[25]  Processing dependent thermal conductivity of nanoporous silica xerogel films , 2002 .

[26]  Kaustav Banerjee,et al.  Modeling and analysis of via hot spots and implications for ULSI interconnect reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[27]  B. C. Daly,et al.  Optical pump and probe measurement of the thermal conductivity of low-k dielectric thin films , 2002 .

[28]  P. Ho,et al.  Porosity effect on the dielectric constant and thermomechanical properties of organosilicate films , 2002 .

[29]  D. Cahill,et al.  Thermal conductivity and sound velocities of hydrogen-silsesquioxane low-k dielectrics , 2002 .

[30]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[31]  Bing-Yue Tsui,et al.  Anisotropic thermal conductivity of nanoporous silica film , 2004, IEEE Transactions on Electron Devices.

[32]  W. Steinhögl,et al.  Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller , 2005 .