A 54.4-mW 4th-order quadrature bandpass CT ΣΔ modulator with 33-MHz BW and 10-bit ENOB for a GNSS receiver

A 4th-order quadrature bandpass continuous-time sigma-delta modulator for a GNSS receiver is presented. With significantly wide bandwidth, the modulator is able to digitalize the down-conversed GNSS signals in two adjacent signal bands simultaneously. This makes it possible to realize simultaneous dual-frequency reception from two satellite systems with one receiver channel instead of two independent channels. A direct RZ feedback is introduced into the input of the last integrator to realize ELD compensation. Power-efficient amplifiers are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-bit quantizers. Implemented in 180nm CMOS, the modulator achieves 62.1dB peak SNDR, 64dB DR and 59.3dB image rejection ratio (IRR), and consumes 54.4mW from a 1.8V power supply.

[1]  Yung-Yu Lin,et al.  A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver , 2011, IEEE Journal of Solid-State Circuits.

[2]  Zhihua Wang,et al.  Dual-mode 10MHz BW 4.8/6.3mW reconfigurable lowpass/complex bandpass CT ΣΔ modulator with 65.8/74.2dB DR for a zero/low-IF SDR receiver , 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

[3]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[4]  Zhihua Wang,et al.  A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[5]  Robert H. M. van Veldhoven,et al.  A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.

[6]  Baoyong Chi,et al.  A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[7]  Baoyong Chi,et al.  A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[8]  David J. Allstot,et al.  A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS , 2010, IEEE Journal of Solid-State Circuits.

[9]  J. Arias,et al.  A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers , 2006, IEEE Journal of Solid-State Circuits.

[10]  Thomas Blon,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .