Energy efficient vedic multiplier design using LVCMOS and HSTL IO standard
暂无分享,去创建一个
[1] N K.,et al. Design A DSP Operations Using Vedic Mathematics , 2014 .
[2] V. Kunchigi,et al. High speed and area efficient vedic multiplier , 2012, 2012 International Conference on Devices, Circuits and Systems (ICDCS).
[3] A. Radhika,et al. FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter , 2013, 2013 International Conference on Energy Efficient Technologies for Sustainability.
[4] Rajesh Mahle,et al. Design a DSP operations using vedic mathematics , 2013, 2013 International Conference on Communication and Signal Processing.
[5] Rutuparna Panda,et al. Speed Comparison of 16x16 Vedic Multipliers , 2011 .
[6] David Blaauw,et al. Leakage Current Reduction in VLSI Systems , 2002, J. Circuits Syst. Comput..
[7] Hamid R. Arabnia,et al. A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics , 2004, ESA/VLSI.
[8] Manisha Pattanaik,et al. Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA , 2013 .
[9] Tanesh Kumar,et al. Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA , 2014, Wirel. Pers. Commun..
[10] Rakshith Saligram,et al. Optimized reversible vedic multipliers for high speed low power operations , 2013, 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES.
[11] Ramesh Pushpangadan,et al. High Speed Vedic Multiplier for Digital Signal Processors , 2009 .
[12] Tanesh Kumar,et al. Design of power optimized memory circuit using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array , 2014, 2014 International Conference on Reliability Optimization and Information Technology (ICROIT).
[13] Ritesh Kumar,et al. A Novel and High Performance Implementation of 8x8 Multiplier based on Vedic Mathematics using 90nm Hybrid PTL /CMOS Logic , 2013 .
[14] Ravindra Patil,et al. Design and implementation of efficient multiplier using Vedic mathematics , 2011, ARTCom 2011.
[15] Tanesh Kumar,et al. LVCMOS I/O standard and drive strength based energy efficient design on ultra scale FPGA , 2013, 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE).
[16] Tanesh Kumar,et al. I/O standard based power optimized processor register design on ultra scale FPGA , 2014, 2014 International Conference on Computing for Sustainable Global Development (INDIACom).