Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering
暂无分享,去创建一个
We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.
[1] H.-S. Philip Wong,et al. Diblock copolymer directed self-assembly for CMOS device fabrication , 2006, SPIE Advanced Lithography.
[2] S. Thompson,et al. Moore's law: the future of Si microelectronics , 2006 .
[3] Craig J Hawker,et al. Defect-free nanoporous thin films from ABC triblock copolymers. , 2006, Journal of the American Chemical Society.