Characterization and development of a thermally enhanced WLFO demonstrator

Current Fan-Out Wafer-Level Packaging technology, WLFO, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As WLFO technology expands to WLSiP (Wafer Level System-in-Package) for very high density system integration, combining multiple chips and different components in the same package, the thermal performance becomes a critical factor. In a broader scope, improving the heat dissipation capabilities opens WLFO technology platform also to power applications. A specific difficulty for all encapsulated packages is that the EMC must be electrical insulator, which challenges both heat conduction and mechanical bonding to a heat spreader. Good heat conductors are, generally, electrical conductors and cannot be used as encapsulate materials. The molding compounds are typically organic resins highly filled with inorganic fillers, but high performance thermal interface material (TIM) are design for metal-metal interfaces, not for organic-metal as required. This paper describes the developments and results achieved towards a Power-FO demonstrator using NANIUM's WLFO technology know-how and manufacturing capabilities. This demonstrator aims the improvement of thermal dissipation capabilities of a typical-size Fan-Out package, by using novel materials, adhesives and assembly processes suitable for high-volume production. It starts from baseline thermal characterization of FO package and the selected measurements methods; discusses the materials and techniques for the coupling of the WLSiP body to a heat spreader; and presents the 8mm × 8mm WLSiP capable of multi-pattern heating and dissipating up to 14W. The work done is part of the collaborative European FP7-ICT project NANOTHERM (Innovative Nano- and Micro Technologies for Advanced Thermo and Mechanical Interfaces), together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/ institutes.

[1]  Kidd Lee,et al.  A hybrid panel embedding process for fanout , 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

[2]  John Hunt,et al.  Synergy between 2.5/3D development and hybrid 3D Wafer Level Fanout , 2012, 2012 4th Electronic System-Integration Technology Conference.

[3]  V. Székely,et al.  Fine structure of heat flow path in semiconductor devices: a measurement and identification method , 1988 .

[4]  V. Szekely,et al.  Identification of RC networks by deconvolution: chances and limits , 1998 .