Evaluation of a software-based error detection technique by RT-level fault injection

This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).

[1]  Y. Savaria,et al.  Software detection mechanisms providing full coverage against single bit-flip faults , 2004, IEEE Transactions on Nuclear Science.

[2]  Massimo Violante,et al.  New techniques for accelerating fault injection in VHDL descriptions , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[3]  E. Normand.  Single-event effects in avionics , 1996 .

[4]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[5]  Massimo Violante,et al.  Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Régis Leveugle,et al.  Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments , 2003, J. Electron. Test..

[7]  S. Rezgui,et al.  Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection , 2000 .

[8]  Régis Leveugle,et al.  On combining fault classification and error propagation analysis in RT-Level dependability evaluation , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[9]  Raoul Velazco,et al.  Injecting bit flip faults by means of a purely software approach: a case studied , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[10]  Pedro J. Gil,et al.  Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System , 1999, EDCC.