A high-speed pipeline architecture of squarer-accumulator (SQAC)

This paper presents a high-speed pipeline architecture for squarer-accumulator (SQAC). The proposed design integrates squarer into multiplier-accumulator (MAC), producing the SQAC, which is utilized widely in signal processing field. The proposed architecture takes advantage of carry-save technique in the accumulation, and utilizes a novel feedback scheme. These ideas could also be applied to improve the performance of MAC. In estimation, the proposal is synthesized with TSMC CMOS libraries of 180nm, 130nm, 90nm and 65nm technology. Simulation results show that our proposed architecture provides almost 50% improvement compared with previous realizations in terms of time and area cost.

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