TRANSIENT AND DELAY ANALYSIS FOR ON-CHIP HIGH SPEED VLSI RLCG INTERCONNECTION NETWORK IN 0.18µm TECHNOLOGY

In this paper, the time domain waveform is approximated for calculation of delay, rise, settling time, damping ratio and natural frequency of a second order RLCG on-chip VLSI interconnect line. It can also be evaluated for multiple interconnect systems but due to harmonics higher order systems are ignored. The model is applied to a single RLCG interconnect line which can also be extended for multi-interconnect systems to analyze crosstalk noise. The model evaluates the performance of a system which is expressed in terms of the transient response due to a unit step input. It is easy to generate and evaluate the delay analytically. A closed form expression for the propagation delay of a CMOS gate driving a distributed RLCG line is introduced. On-chip inductance and conductance are expected to have a profound effect on traditional high performance IC design methodologies. In the proposed model, it is shown that when the value of G is increased, the time at which the rise time, settling time and the time when the steady state condition is reached are all increased. So, for high speed circuits one must increase the value of G so that the steady state condition is reached quickly and it is also shown that with the increase in the value of G the delay will reduce. The simulation results performed in SPICE environment justify the efficacy of the proposed model.

[1]  Mark Horowitz,et al.  Timing Models for MOS Circuits , 1983 .

[2]  Rajib Kar,et al.  An Explicit Delay Model for On-Chip VLSI RLC Interconnect , 2011, 2011 International Conference on Devices and Communications (ICDeCom).

[3]  Shien-Yang Wu,et al.  Analysis of interconnect delay for 0.18 /spl mu/m technology and beyond , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[4]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[5]  S. Nikolaidis,et al.  Delay and power estimation for a CMOS inverter driving RC interconnect loads , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[6]  Rajib Kar,et al.  Accurate Crosstalk Analysis for RLC On-Chip , 2011 .

[7]  G. Matthaei.  Modern transmission line theory and applications , 1981, Proceedings of the IEEE.

[8]  Rajib Kar,et al.  Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects , 2011, 2011 International Conference on Devices and Communications (ICDeCom).

[9]  Rajib Kar,et al.  A NOVEL CIRCUIT REDUCTION TECHNIQUE TO DETERMINE THE RESPONSE OF THE ON-CHIP VLSI RC INTERCONNECT FOR RAMP INPUT EXCITATION , 2011 .

[10]  Rajib Kar,et al.  Explicit Delay and Power Estimation Method for CMOS Inverter Driving on-Chip RLC Interconnect Load , 2011 .

[11]  Rajib Kar,et al.  CLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INVERTER DRIVING RLC INTERCONNECT UNDER STEP INPUT , 2011 .

[12]  Rajib Kar,et al.  Unified delay analysis for on-chip RLCG interconnects for ramp input using fourth order transfer function , 2010, 2010 International Conference on Signal and Image Processing.

[13]  Rajib Kar,et al.  An explicit model for delay and rise time for distributed RC on-chip VLSI interconnect , 2010, 2010 International Conference on Signal and Image Processing.

[14]  V. Maheshwari,et al.  AN EXPLICIT CROSSTALK AWARE DELAY MODELLING FOR ON-CHIP VLSI RLC INTERCONNECT WITH SKIN EFFECT , 2011 .

[15]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .