A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors

A 14b 70MS/s 3-stage pipeline ADC in a 0.13mum CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a 0.35mum minimum channel length for 2.5V system applications shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB at 14b, occupies a die area of 3.3mm2, and consumes 235mW at 70MS/s

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