On testing of non-isolated embedded legacy cores and their surround logic

We consider issues related to the testing of a legacy core embedded in user-defined logic. We assume that the only information available about the core is its test set. We provide procedures for testing the core and its surrounding logic without adding DFT logic. The procedures maximize the information extracted from the test set given for the core, in order to maximize the fault coverage achieved without DFT. We also describe DFT insertion procedures. The core and the surrounding logic are considered simultaneously during DFT insertion to minimize the amount of DFT logic required.