A sparse macromodeling method for RC interconnect multiports

This paper describes a technique for generating sparse RC interconnect macromodels. By inserting an artificial delay in the transconductance between distant port nodes, the technique can dramatically sparsify the time domain stencil of the N-port macromodel. The error introduced is measured in terms of the poles and residues of the RC circuit, thereby allowing accuracy vs. sparsity trade-offs to be made. Some examples are shown that demonstrate no noticeable loss of accuracy for significant improvements in sparsity.