Leakage Reduction by Modified Stacking and Optimum ISO Input Loading in CMOS Devices

In this paper, we have considered different circuit techniques to reduce leakage currents in digital CMOS circuits. In this study, an emphasis is given on gate leakage and sub threshold components of leakage currents. The leakage currents of 65 nm and 45 nm technology node NMOS/PMOS transistor and simple CMOS inverter are compared with low leakage current circuits. The modified stack forcing scheme with optimum iso input load condition gave leakage reduction by a factor of 7 compared to the normal stack forcing technique.

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