Adaptive caches as a defense mechanism against cache side-channel attacks
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[1] Pepe Vila,et al. Theory and Practice of Finding Eviction Sets , 2018, 2019 IEEE Symposium on Security and Privacy (SP).
[2] Nael B. Abu-Ghazaleh,et al. Jump over ASLR: Attacking branch predictors to bypass ASLR , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[3] Adi Shamir,et al. Cache Attacks and Countermeasures: The Case of AES , 2006, CT-RSA.
[4] Marco Chiappetta,et al. Real time detection of cache-based side-channel attacks using hardware performance counters , 2016, Appl. Soft Comput..
[5] Michael K. Reiter,et al. Cross-VM side channels and their use to extract private keys , 2012, CCS.
[6] Klaus Wagner,et al. Flush+Flush: A Fast and Stealthy Cache Attack , 2015, DIMVA.
[7] Gernot Heiser,et al. Last-Level Cache Side-Channel Attacks are Practical , 2015, 2015 IEEE Symposium on Security and Privacy.
[8] Frank Vahid,et al. A highly configurable cache architecture for embedded systems , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..
[9] Jean-Marc Menaud,et al. Cache-based side-channel attacks detection through Intel Cache Monitoring Technology and Hardware Performance Counters , 2018, 2018 Third International Conference on Fog and Mobile Edge Computing (FMEC).
[10] Yuval Yarom,et al. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack , 2014, USENIX Security Symposium.
[11] Xiaolin Gui,et al. An approach with two-stage mode to detect cache-based side channel attacks , 2013, The International Conference on Information Networking 2013 (ICOIN).
[12] Tosiron Adegbija,et al. Exploiting Configurability as a Defense against Cache Side Channel Attacks , 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
[13] Toon Verwaest,et al. Spectre is here to stay: An analysis of side-channels and speculative execution , 2019, ArXiv.
[14] Ahmad Patooghy,et al. Janus: An uncertain cache architecture to cope with side channel attacks , 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).
[15] Yuval Yarom,et al. CacheBleed: a timing attack on OpenSSL constant-time RSA , 2016, Journal of Cryptographic Engineering.
[16] Ruby B. Lee,et al. A novel cache architecture with enhanced performance and security , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[17] Nael B. Abu-Ghazaleh,et al. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks , 2012, TACO.
[18] Thomas F. Wenisch,et al. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution , 2018, USENIX Security Symposium.
[19] Michael Hamburg,et al. Spectre Attacks: Exploiting Speculative Execution , 2018, 2019 IEEE Symposium on Security and Privacy (SP).
[20] Ruby B. Lee,et al. New cache designs for thwarting software cache-based side channel attacks , 2007, ISCA '07.
[21] Daniel J. Bernstein,et al. Cache-timing attacks on AES , 2005 .
[22] Colin Percival. CACHE MISSING FOR FUN AND PROFIT , 2005 .
[23] Angelos D. Keromytis,et al. The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications , 2015, CCS.
[24] Michel A. Kinsy,et al. BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox , 2019, FPGA.
[25] Carsten Willems,et al. Practical Timing Side Channel Attacks against Kernel Space ASLR , 2013, 2013 IEEE Symposium on Security and Privacy.