Interconnect effects in deep submicron implementation of high performance arithmetic architectures

The conventional trend in algorithm implementation has been the reliance on advancements in process technology in order to satisfy the ever-increasing demand for high-speed processors, and computational systems. As current device technology approaches sub-100nm minimum device size, not only does the device geometry decrease, but switching times, and operating voltages also scale down. These gains come at the expense of increased layout complexity, and a greater susceptibility to parasitic effects in the interconnections. In this paper we will briefly overview the challenges that digital designers will have to face in the imminent future, and will provide suggestions on algorithmic measures which may be taken in order to overcome some of these obstacles. To illustrate our point, we will present an analysis of a digital multiplication algorithm, which is predicted to outperform current schemes, for future technologies.

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