VLSI implementation of adaptive bit/serial IIR filters

A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2- mu m CMOS technology clocked at 50 MHz.<<ETX>>

[1]  S. C. Knowles,et al.  Bit-level systolic arrays for IIR filtering , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[2]  Peter B. Denyer,et al.  VLSI Signal Processing: A Bit-Serial Approach , 1985 .

[3]  Roger Woods,et al.  Systolic IIR filters with bit level pipelining , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

[4]  J. Vuillemin,et al.  Recursive implementation of optimal time VLSi integer multipliers , 1984 .

[5]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[6]  John G. McWhirter,et al.  Some Systolic Array Developments in the United Kingdom , 1987, Computer.

[7]  A. Corry,et al.  Architecture of a CMOS correlator , 1983 .