Resource sharing in CMOS SPAD arrays: application requirements and design solutions

The great potential of Single-Photon Avalanche Diodes (SPAD) co-integrated with CMOS electronics is still far to be fully exploited, mainly due to technological constraints. Since many applications require power-hungry time-tagging circuits with picosecond resolution, sharing readout channels among many SPADs is compulsory to improve sensor efficiency and reduce problems related to power consumption. This paper summarizes the techniques proposed so far to share resources in SPAD arrays, describing several key circuit blocks used in advanced architectures designed for different application domains. The current state of the art, together with future promising directions fostered by 3D integration technologies, is reviewed.

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