Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM technology are the small read window because of the low tunnel magnetic resistance (TMR) ratio, and the low read current due to read disturb, which is proportional to the bitline (BL) voltage [1].

[1]  Meng-Fan Chang,et al.  An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Heinz Hoenigschmid,et al.  Signal-Margin-Screening for Multi-Mb MRAM , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[4]  Shoji Ikeda,et al.  A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme , 2010, IEEE Journal of Solid-State Circuits.

[5]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).