TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance.

[1]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2008, 2008 IEEE International Conference on Computer Design.

[2]  Sandip Kundu,et al.  An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors , 2011, 2011 Asian Test Symposium.

[3]  Vance W. Berger,et al.  Trend Tests for Counts and Proportions , 2005 .

[4]  Ding-Ming Kwai,et al.  On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding , 2010, 2010 28th VLSI Test Symposium (VTS).

[5]  Sung Kyu Lim,et al.  Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[6]  Li Yu.  A Study of Through-Silicon-Via ( TSV ) Induced Transistor Variation by , 2011 .

[7]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[8]  Fangming Ye,et al.  TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.

[9]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[10]  Tai-Hong Chen,et al.  Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[11]  Peter Ramm,et al.  Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .

[12]  Mitsumasa Koyanagi,et al.  Handbook of 3D Integration , 2008 .

[13]  Mitsumasa Koyanagi,et al.  High density Cu-TSVs and reliability issues , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[14]  TingTing Hwang,et al.  TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[15]  Hsien-Hsin S. Lee,et al.  Testing Circuit-Partitioned 3D IC Designs , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[16]  Mark Mohammad Tehranipoor,et al.  High-quality pattern selection for screening small-delay defects considering process variations and crosstalk , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.

[18]  Hsien-Hsin S. Lee,et al.  Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  K. Vaidyanathan,et al.  Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps , 2008, 2008 58th Electronic Components and Technology Conference.

[20]  Yuan Xie,et al.  Design space exploration for 3D architectures , 2006, JETC.

[21]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[22]  Erik Jan Marinissen,et al.  Optimization methods for post-bond die-internal/external testing in 3D stacked ICs , 2010, 2010 IEEE International Test Conference.

[23]  Erik Jan Marinissen,et al.  Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Erik Jan Marinissen.  Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[25]  Jae-Seok Yang.  Nanometer VLSI design-manufacturing interface for large scale integration , 2011 .

[26]  Mario H. Konijnenburg,et al.  A structured and scalable test access architecture for TSV-based 3D stacked ICs , 2010, 2010 28th VLSI Test Symposium (VTS).

[27]  Fan Zhang,et al.  Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods , 2012, J. Electron. Test..

[28]  Gyujei Lee,et al.  Mechanical characterization of residual stress around TSV through instrumented indentation algorithm , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[29]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[30]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[31]  Weiping Shi,et al.  A circuit level fault model for resistive bridges , 2003, TODE.

[32]  Qiang Xu,et al.  On effective TSV repair for 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[33]  Ken Suzuki,et al.  Mechanical and electrical reliability of copper interconnections for 3DIC , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[34]  D. Malta,et al.  Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[35]  Diederik Verkest,et al.  Analysis of microbump induced stress effects in 3D stacked IC technologies , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[36]  Yu Cao,et al.  Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Shi-Yu Huang,et al.  Performance Characterization of TSV in 3D IC via Sensitivity Analysis , 2010, 2010 19th IEEE Asian Test Symposium.

[38]  Qiang Xu,et al.  Test architecture design and optimization for three-dimensional SoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[39]  W. Dehaene,et al.  Test structures for characterization of through silicon vias , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

[40]  Krishnendu Chakrabarty,et al.  Pre-bond probing of TSVs in 3D stacked ICs , 2011, 2011 IEEE International Test Conference.

[41]  Erik Jan Marinissen,et al.  Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base , 2011, 2011 Asian Test Symposium.

[42]  Yuan Xie.  Processor Architecture Design Using 3D Integration Technology , 2010, 2010 23rd International Conference on VLSI Design.

[43]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[44]  Paul S. Ho,et al.  Thermomechanical reliability of through-silicon vias in 3D interconnects , 2011, 2011 International Reliability Physics Symposium.

[45]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[46]  Hsien-Hsin S. Lee,et al.  A scanisland based design enabling prebond testability in die-stacked microprocessors , 2007, 2007 IEEE International Test Conference.

[47]  Jiwoo Pak,et al.  Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[48]  Paul D. Franzon,et al.  Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC , 2009, 2009 IEEE International Conference on 3D System Integration.

[49]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.

[50]  Suk-kyu Ryu,et al.  Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[51]  Erik Jan Marinissen,et al.  Optimization Methods for Post-Bond Testing of 3D Stacked ICs , 2012, J. Electron. Test..

[52]  C. Laviron,et al.  Via first approach optimisation for Through Silicon Via applications , 2009, 2009 59th Electronic Components and Technology Conference.

[53]  A. Jourdain,et al.  3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.

[54]  So-Ra Kim,et al.  8Gb 3D DDR3 DRAM using through-silicon-via technology , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[55]  Albrecht Uhlig,et al.  Filling TSV of different dimension using galvanic copper deposition , 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

[56]  Jiwoo Pak,et al.  Modeling of electromigration in through-silicon-via based 3D IC , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[57]  Sung Kyu Lim,et al.  Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[58]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[59]  Bashir M. Al-Hashimi,et al.  Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs , 2011, 2011 Asian Test Symposium.

[60]  Qiang Xu,et al.  Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.