论文信息 - Delay and Power Optimization in VLSI Circuits

Delay and Power Optimization in VLSI Circuits

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

Lance A. Glasser | Lennox Hoyte

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