Symbolic system level reliability analysis

More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such complex systems in terms of monetary costs, power consumption, reliability etc. demands for new analysis approaches at the electronic system level. In this paper, two symbolic system level reliability analysis approaches are introduced. First, a formal approach based on Binary Decision Diagrams is presented that allows to calculate exact reliability measures for small to moderate-sized systems. Second, a simulative approach is presented that hybridizes a Monte Carlo simulation with a SAT solver and delivers adequate approximations of the reliability measures for large and complex systems.

[1]  Martin Lukasiewycz,et al.  Incorporating graceful degradation into embedded system design , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  G. S. Tseitin On the Complexity of Derivation in Propositional Calculus , 1983 .

[3]  Martin Lukasiewycz,et al.  Interactive presentation: Reliability-aware system synthesis , 2007 .

[4]  Martin Lukasiewycz,et al.  Exploiting data-redundancy in reliability-aware networked embedded system design , 2009, CODES+ISSS '09.

[5]  Martin Lukasiewycz,et al.  Reliability-Aware System Synthesis , 2007 .

[6]  Christian Haubelt,et al.  SAT-based techniques in system synthesis , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[8]  Martin Lukasiewycz,et al.  Symbolic Reliability Analysis of Self-healing Networked Embedded Systems , 2008, SAFECOMP.

[9]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[10]  Martin Lukasiewycz,et al.  Symbolic voter placement for dependability-aware system synthesis , 2008, CODES+ISSS '08.

[11]  Antoine Rauzy,et al.  New algorithms for fault trees analysis , 1993 .

[12]  Martin Lukasiewycz,et al.  Symbolic Reliability Analysis and Optimization of ECU Networks , 2008, 2008 Design, Automation and Test in Europe.

[13]  Martin Lukasiewycz,et al.  Towards scalable system-level reliability analysis , 2010, Design Automation Conference.

[14]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[15]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[16]  Petru Eles,et al.  Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Li Shang,et al.  Application-Specific MPSoC Reliability Optimization , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[19]  Martin Lukasiewycz,et al.  Combined system synthesis and communication architecture exploration for MPSoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Alessandro Birolini Reliability Engineering: Theory and Practice , 1999 .