A New Memory-Disk Integrated System with HW Optimizer

Current high-performance computer systems utilize a memory hierarchy of on-chip cache, main memory, and secondary storage due to differences in device characteristics. Limiting the amount of main memory causes page swap operations and duplicates data between the main memory and the storage device. The characteristics of next-generation memory, such as nonvolatility, byte addressability, and scaling to greater capacity, can be used to solve these problems. Simple replacement of secondary storage with new forms of nonvolatile memory in a traditional memory hierarchy still causes typical problems, such as memory bottleneck, page swaps, and write overhead. Thus, we suggest a single architecture that merges the main memory and secondary storage into a system called a Memory-Disk Integrated System (MDIS). The MDIS architecture is composed of a virtually decoupled NVRAM and a nonvolatile memory performance optimizer combining hardware and software to support this system. The virtually decoupled NVRAM module can support conventional main memory and disk storage operations logically without data duplication and can reduce write operations to the NVRAM. To increase the lifetime and optimize the performance of this NVRAM, another hardware module called a Nonvolatile Performance Optimizer (NVPO) is used that is composed of four small buffers. The NVPO exploits spatial and temporal characteristics of static/dynamic data based on program execution characteristics. Enhanced virtual memory management and address translation modules in the operating system can support these hardware components to achieve a seamless memory-storage environment. Our experimental results show that the proposed architecture can improve execution time by about 89% over a conventional DRAM main memory/HDD storage system, and 77% over a state-of-the-art PRAM main memory/HDD disk system with DRAM buffer. Also, the lifetime of the virtually decoupled NVRAM is estimated to be 40% longer than that of a traditional hierarchy based on the same device technology.

[1]  Yuan Xie,et al.  A frequent-value based PRAM memory architecture , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[2]  Hi-Seok Kim,et al.  PRAM and NAND flash hybrid architecture based on hot data detection , 2010, 2010 2nd International Conference on Mechanical and Electronics Engineering.

[3]  Andy Rudoff.  Programming Models for Emerging Non-Volatile Memory Technologies , 2013, login Usenix Mag..

[4]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[5]  Ki-Whan Song,et al.  A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW , 2011, 2011 IEEE International Solid-State Circuits Conference.

[6]  Jun Yang,et al.  A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.

[7]  Shuichi Oikawa.  Adapting byte addressable memory storage to user-level file system services , 2014, RACS '14.

[8]  Jun Yang,et al.  Improving write operations in MLC phase change memory , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[9]  Shin-Dug Kim,et al.  Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory , 2015, Comput. J..

[10]  Tei-Wei Kuo,et al.  A PCM translation layer for integrated memory and storage management , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[11]  Shin-Dug Kim,et al.  An integrated memory-disk system with buffering adapter and non-volatile memory , 2013, Des. Autom. Embed. Syst..

[12]  In-Sung Choi,et al.  A dynamic adaptive converter and management for PRAM-based main memory , 2013, Microprocess. Microsystems.

[13]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[14]  Zhao Zhang,et al.  Design and optimization of large size and low overhead off-chip caches , 2004, IEEE Transactions on Computers.

[15]  Gavin Brown,et al.  Garbage collection auto-tuning for Java mapreduce on multi-cores , 2011, ISMM '11.

[16]  Ferdinando Bedeschi,et al.  A Multi-Level-Cell Bipolar-Selected Phase-Change Memory , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[17]  Kyu Ho Park,et al.  Adaptive page grouping for energy efficiency in hybrid PRAM-DRAM main memory , 2012, RACS.

[18]  Lizy Kurian John,et al.  Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite , 2007, ISCA '07.

[19]  Shuichi Oikawa,et al.  Integrating memory management with a file system on a non-volatile main memory system , 2013, SAC '13.

[20]  Tajana Simunic,et al.  PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[21]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[22]  Rami G. Melhem,et al.  Using PCM in Next-generation Embedded Space Applications , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.

[23]  A. L. Narasimha Reddy,et al.  SCMFS: A file system for Storage Class Memory , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[24]  Sangyeun Cho,et al.  Memorage: emerging persistent RAM based malleable main memory and storage architecture , 2013, ICS '13.

[25]  Yiran Chen,et al.  Emerging non-volatile memories: Opportunities and challenges , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[26]  John L. Henning.  SPEC CPU2006 benchmark descriptions , 2006, CARN.

[27]  Jeffrey Katcher,et al.  PostMark: A New File System Benchmark , 1997 .