Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters

This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point two's-complement equivalents.

[1]  Tzi-Dar Chiueh,et al.  A Low-Power Digit-Based Reconfigurable FIR Filter , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Graham A. Jullien,et al.  Theory and Applications of the Double-Base Number System , 1999, IEEE Trans. Computers.

[3]  Narayanan Vijaykrishnan,et al.  Power-efficient implementation of turbo decoder in SDR system , 2004, IEEE International SOC Conference, 2004. Proceedings..

[4]  Sunil P. Khatri,et al.  A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Haridimos T. Vergos,et al.  Modulo 2n±1 Adder Design Using Select-Prefix Blocks , 2003, IEEE Trans. Computers.

[6]  Vassilis Paliouras,et al.  Low-Power Digital Filtering Based on the Logarithmic Number System , 2007, PATMOS.

[7]  Roberto Muscedere,et al.  Efficient techniques for binary-to-multidigit multidimensional logarithmic number system conversion using range-addressable look-up tables , 2005, IEEE Transactions on Computers.

[8]  Vassilis Paliouras,et al.  Low-power properties of the logarithmic number system , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[9]  Earl E. Swartzlander,et al.  The Sign/Logarithm Number System , 1975, IEEE Transactions on Computers.

[10]  Vassilis Paliouras,et al.  A novel algorithm for accurate logarithmic number system subtraction , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[11]  Mark G. Arnold,et al.  Applying Features of IEEE 754 to Sign/Logarithm Arithmetic , 1992, IEEE Trans. Computers.

[12]  I. Miller.  Probability, Random Variables, and Stochastic Processes , 1966 .

[13]  D.V.S. Chandra.  Error analysis of FIR filters implemented using logarithmic arithmetic , 1998 .

[14]  Sylvain Collange,et al.  Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction , 2007 .

[15]  Vassilis Paliouras,et al.  A novel algorithm for multi-operand logarithmic number system addition and subtraction using polynomial approximation , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[16]  Earl E. Swartzlander,et al.  Power-delay characteristics of CMOS multipliers , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[17]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .

[18]  Mark G. Arnold,et al.  Arithmetic co-transformations in the real and complex logarithmic number systems , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[19]  Sylvain Collange,et al.  A Real/Complex Logarithmic Number System ALU , 2011, IEEE Transactions on Computers.

[20]  David M. Lewis,et al.  Algorithm design for a 30-bit integrated logarithmic processor , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[21]  Arda Yurdakul,et al.  An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  T. J. Sullivan,et al.  VLSI based design of a battery-operated digital hearing aid , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

[23]  Fred J. Taylor,et al.  A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.

[24]  Chip-Hong Chang,et al.  Information Theoretic Approach to Complexity Reduction of FIR Filter Design , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  J. N. Coleman.  Simplification of table structure in logarithmic arithmetic , 1995 .

[26]  Lars Wanhammar,et al.  Implementation of elementary functions for logarithmic number systems , 2008, IET Comput. Digit. Tech..

[27]  Vassilis Paliouras,et al.  Considering the alternatives in low-power design , 2001 .

[28]  Mark Horowitz,et al.  Energy-Efficient Floating-Point Unit Design , 2011, IEEE Transactions on Computers.

[29]  Mary Jane Irwin,et al.  Number representations for reducing switched capacitance in subband coding , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[30]  Florent de Dinechin,et al.  Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[31]  Hao Wang,et al.  Improved Log-MAP decoding algorithm for turbo-like codes , 2006, IEEE Communications Letters.

[32]  Jean-Michel Muller,et al.  Elementary Functions: Algorithms and Implementation , 1997 .

[33]  Mark G. Arnold.  Reduced power consumption for MPEG decoding with LNS , 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.

[34]  Patrick Robertson,et al.  A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain , 1995, Proceedings IEEE International Conference on Communications ICC '95.

[35]  H. Henkel.  Improved addition for the logarithmic number system , 1989, IEEE Trans. Acoust. Speech Signal Process..

[36]  T. Kurokawa,et al.  Error analysis of recursive digital filters implemented with logarithmic number systems , 1980 .

[37]  V. Mahalingam,et al.  Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition , 2006, IEEE Transactions on Computers.

[38]  Vassilis Paliouras,et al.  Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters , 2013, IEEE Trans. Computers.

[39]  Vassilis Paliouras,et al.  Logarithmic Number System for Low-Power Arithmetic , 2000, PATMOS.

[40]  Rizalafande Che Ismail,et al.  ROM-less LNS , 2011, 2011 IEEE 20th Symposium on Computer Arithmetic.

[41]  Rong-Rong Chen,et al.  WLC45-2: Application of Nonbinary LDPC Codes for Communication over Fading Channels Using Higher Order Modulations , 2006, IEEE Globecom 2006.

[42]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[43]  Jirí Kadlec,et al.  The European Logarithmic Microprocesor , 2008, IEEE Transactions on Computers.

[44]  Wayne Luk,et al.  FPGA Designs with Optimized Logarithmic Arithmetic , 2010, IEEE Transactions on Computers.