Design of switching frequency limiter for hysteresis current controlled PWM VSI

Stable operation of hysteresis control of the inverter output current can be guaranteed by considering the system parameter, the supply voltage and the minimum onJoff time when determining the hysteresis band. In the paper, we will discuss the characteristics of hysteresis current control and the role of frequency limiter, implement digital circuit for controlling the hysteresis and limiting the switching frequency on the FPGA base, design the frequency limiter which shows stable operation by guaranteeing the minimum on time and off time of the switching device while robust to the load changes, and compare the performance of the proposed hysteresis current control characteristics with the existing scheme.