Ultimate CMOS ULSI performance

Ultra-Large-Scale Integration (ULSI) CMOS technology is advancing beyond the realm of conventional scaling theory, requiring a new approach to the problem of scale reduction. Limits on active power are pushing the power supply voltage, V/sub DD/, downward, while increased MOSFET count is creating pressure to increase threshold-voltage, V/sub T/, to keep passive power (sub-threshold leakage) from growing. A conflict between the needs for lower V/sub DD/ and higher V/sub T/ thus arises. Power constraints alone, independent of other potential limitations, will lead to maximum performance at the 100-nm lithographic scale of approximately two to three times that of 0.5-/spl mu/m, 3.3 V CMOS technology.<<ETX>>