Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers

The multipliers modules tend to be the most significant in performance, circuit area, energy, and power in digital circuits of DSP (Digital Signal Processing). In the literature, several works seek to find the best multiplier for one specific constraint. However, an efficient design of hardwired parallel array multipliers depends directly on the project constraints. This work proposes a framework to efficiently generalize and explore different compositions of arithmetic operators with an emphasis on parallel binary multipliers, guiding the designer through the micro-architecture development. Two radix-4 multipliers were synthesized in a commercial 65 nm technology to evaluate the framework-generated designs.

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