Efficient VLSI Power/Ground Network Sizing Based on Equivalent Circuit Modeling

We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to the reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout as done pre- viously, the new method first constructs a reduced but electrically equivalent P/G network. Then the sequence of linear program- ming method is applied to optimize the reduced network. The solu- tion of the original network is then back solved from the optimized reduced network. The new method exploits the regularities in the P/G networks to reduce the complexities of P/G networks. Exper- imental results show that the sizes of reduced networks are typi- cally significantly smaller than that of the original networks. The resulting algorithm is fast enough that P/G networks with more than one million branches can be sized in a few minutes on mod- ern SUN workstations.