On-chip feature extraction for spike sorting in high density implantable neural recording systems

Modern microelectrode arrays acquire neural signals from hundreds of neurons in parallel that are subsequently processed for spike sorting. It is important to identify, extract and transmit appropriate features that allow accurate spike sorting while using minimum computational resources. This paper describes a new set of spike sorting features, explicitly framed to be computationally efficient and shown to outperform PCA based spike sorting. A hardware friendly architecture, feasible for implantation, is also presented for detecting neural spikes and extracting features to be transmitted for off chip spike classification.

[1]  J.C. Sanchez,et al.  A Pulse-Based Feature Extractor for Spike Sorting Neural Signals , 2007, 2007 3rd International IEEE/EMBS Conference on Neural Engineering.

[2]  A. Zviagintsev,et al.  Low-Power Architectures for Spike Sorting , 2005, Conference Proceedings. 2nd International IEEE EMBS Conference on Neural Engineering, 2005..

[3]  M. Aghagolzadeh,et al.  Compressed and Distributed Sensing of Neuronal Activity for Real Time Spike Train Decoding , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[4]  K.V. Shenoy,et al.  Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems , 2005, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[5]  Dejan Markovic,et al.  Comparison of spike-sorting algorithms for future hardware implementation , 2008, 2008 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

[6]  Khalil Najafi,et al.  Towards a button-sized 1024-site wireless cortical microstimulating array , 2003 .

[7]  Awais M. Kamboh,et al.  Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics , 2007, IEEE Transactions on Biomedical Circuits and Systems.