Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.

[1]  Ivica Manic,et al.  Effects of electrical stressing in power VDMOSFETs , 2005, Microelectron. Reliab..

[2]  Daniel M. Fleetwood,et al.  Effects of hydrogen transport and reactions on microelectronics radiation response and reliability , 2002, Microelectron. Reliab..

[3]  C. R. Helms,et al.  The silicon-silicon dioxide system: Its microstructure and imperfections , 1994 .

[4]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[5]  Aleksandar B. Jakšić,et al.  Analysis of postirradiation annealing of n-channel power vertical double-diffused metal-oxide-semiconductor transistors , 2000 .

[6]  S. Gamerith,et al.  Negative bias temperature stress on low voltage p-channel DMOS transistors and the role of nitrogen , 2002, Microelectron. Reliab..

[7]  Shigeo Ogawa,et al.  Interface‐trap generation at ultrathin SiO2 (4–6 nm)‐Si interfaces during negative‐bias temperature aging , 1995 .

[8]  P. De Pauw,et al.  Bias temperature reliability of p-channel high-voltage devices , 1997 .

[9]  Ninoslav Stojadinovic,et al.  Analysis of gamma-radiation induced instability mechanisms in CMOS transistors , 1989 .

[10]  Zhijian Yang,et al.  Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs , 2002 .

[11]  Ivica Manic,et al.  Effects of high electric field and elevated-temperature bias stressing on radiation response in power VDMOSFETs , 2002, Microelectron. Reliab..

[12]  H. L. Hughes,et al.  Annealing of total dose damage: redistribution of interface state density on [100], [110] and [111] orientation silicon , 1988 .

[13]  P. Habas,et al.  Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs , 1996 .

[14]  Ivica Manic,et al.  Effects of burn-in stressing on radiation response of power VDMOSFETs , 2002 .

[15]  P. Winokur,et al.  Simple technique for separating the effects of interface traps and trapped‐oxide charge in metal‐oxide‐semiconductor transistors , 1986 .