MHz-rate Multi-Antenna Decoders: Dedicated SVD Chip Example

This chapter will demonstrate hardware realization of multidimensional signal processing. The emphasis is on managing design complexity and minimizing power and area for complex signal processing algorithms. As an example, adaptive algorithm for singular value decomposition will be used. Power and area efficiency derived from this example will also be used as a reference for flexibility considerations in Chap. 15.

[1]  Robert W. Brodersen,et al.  An adaptive multiantenna transceiver for slowly flat fading channels , 2003, IEEE Trans. Commun..

[2]  Y. Naito,et al.  An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[3]  R.W. Brodersen,et al.  A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/ , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[4]  S. Menzl,et al.  A 720 /spl mu/W 50 MOPs 1V DSP for a hearing aid chip set , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[5]  G. Troster,et al.  A high precision 1024-point FFT processor for 2D convolution , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[6]  A. Varadharajan,et al.  A low-cost 300 MHz RISC CPU with attached media processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[7]  J.L. van Meerbergen,et al.  Heterogeneous multiprocessor for the management of real-time video and graphics streams , 2000, IEEE Journal of Solid-State Circuits.

[8]  Dejan Markovic,et al.  Power and Area Minimization for Multidimensional Signal Processing , 2007, IEEE Journal of Solid-State Circuits.

[9]  E. Sackinger,et al.  A 3.2 GOPS multiprocessor DSP for communication applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  Fumio Arakawa,et al.  SH-X: an embedded processor core for consumer appliances , 2005, SIGARCH Comput. Archit. News.

[11]  Gerard J. Foschini,et al.  Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas , 1996, Bell Labs Technical Journal.

[12]  Siavash M. Alamouti,et al.  A simple transmit diversity technique for wireless communications , 1998, IEEE J. Sel. Areas Commun..

[13]  Lizhong Zheng,et al.  Diversity and multiplexing: a fundamental tradeoff in multiple-antenna channels , 2003, IEEE Trans. Inf. Theory.