A reconfigurable decision-feedback equalizer chip set architecture for high bit-rate QAM digital modems

A 70-MHz decision-feedback equalizer chip set using novel architecture and circuit design techniques that can accommodate a wide variety of modulation formats (QPSK, 16-, 64-, 256-QAM) is proposed. The equalizer is configurable into either a symbol-spaced or fractionally spaced structure. The CMOS chips are full cascadable to implement longer filter lengths without any speed degradation, and the coefficient updating circuitry for implementing the LMS algorithm is included on-chip.<<ETX>>

[1]  M. Schobinger,et al.  CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems , 1990, IEEE International Symposium on Circuits and Systems.

[2]  H. Samueli,et al.  A high-speed CMOS full-adder cell using a new circuit design technique-adaptively-biased pseudo-NMOS logic , 1990, IEEE International Symposium on Circuits and Systems.

[3]  Keshab K. Parhi.  High-speed architectures for algorithms with quantizer loops , 1990, IEEE International Symposium on Circuits and Systems.

[4]  U. Kleine,et al.  Wave digital filters using carry-save arithmetic , 1988, 1988., IEEE International Symposium on Circuits and Systems.