Memory efficient FPGA implementation for flooded LDPC decoder

This paper proposes an FPGA based flooded architecture for quasi-cyclic (QC) LDPC decoder. The message computation for both check and variable node update is done using a parallel scheme of a number of processing units equal to the expansion factor of the QC matrix. The proposed architecture performs serial processing of the messages by dedicated check node and variable node processing units. This way, a reduced memory word size is used, which lead to a reduction of the BRAM blocks. Multiple frame decoding is used in order to both increase the throughput and to increase the BRAM usage. Implementation results for the WiMAX (1152, 2304) QC irregular LDPC code indicate that the proposed architecture has up to 4x less slices resource utilization and up to 1 order of magnitude less BRAM blocks with respect to other flooded architectures, while maintaining a throughput of several hundreds of Mbps.

[1]  David Declercq,et al.  Min-Sum-based decoders running on noisy hardware , 2013, 2013 IEEE Global Communications Conference (GLOBECOM).

[2]  Ning Chen,et al.  Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Manabu Hagiwara,et al.  Comment on "Quasi-Cyclic Low Density Parity Check Codes From Circulant Permutation Matrices" , 2009, IEEE Trans. Inf. Theory.

[4]  T. Sansaloni,et al.  Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[5]  Shu Lin,et al.  Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Rüdiger L. Urbanke,et al.  The renaissance of Gallager's low-density parity-check codes , 2003, IEEE Commun. Mag..

[7]  Vikram Arkalgud Chandrasetty,et al.  An area efficient LDPC decoder using a reduced complexity min-sum algorithm , 2012, Integr..

[8]  Alexios Balatsoukas-Stimming,et al.  FPGA-based design and implementation of a multi-GBPS LDPC decoder , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[9]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  David Blaauw,et al.  Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM , 2014, IEEE Journal of Solid-State Circuits.

[11]  Marc P. C. Fossorier,et al.  Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices , 2004, IEEE Trans. Inf. Theory.