Checking temporal properties under simulation of executable system descriptions

The verification of systems, i.e., hardware or hardware/software systems, is an important task in the design process. More than 70% of the development time is spend for locating and correcting error in the design. Therefore, many techniques have been proposed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is curl-entry restricted to small or medium sized designs of to a specific phase in the design cycle. In this paper, we present a method for verifying temporal properties of systems described in an executable description language. Our method allows the user to specify properties about the system in finite linear time temporal logic (FLTL). These properties are checked on-the-fly during each simulation run, and each violation is immediately indicated to the designer.