论文信息 - Integrator-chain multiplier

Integrator-chain multiplier

An MVL (multiple-valued-logic) multiplier circuit scheme, called the integrator-chain method, is presented. This circuit scheme is particularly suited to the switched-capacitor topology. The feasibility of circuit implementations of the integrator-chain multiplier design in various number systems, including the sign-bit number representation, the R's and (R-1)'s complement representations, and the signed-digit-number (SDN) system, is discussed. It is demonstrated by simulation that a 4*4 multiplier circuit operating in a radix-7 SDN system has a size comparable to the simplest binary counterpart.<<ETX>>

Kenneth C. Smith | Hsu Liang Ho

[1] Kenneth C. Smith,et al. Switched capacitor circuits in the implementation of multiple-valued logic , 1989, Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic.

[3] Ivan Flores,et al. The logic of computer arithmetic , 1963 .

[4] P. R. Gray,et al. Reference refreshing cyclic analog-to-digital and digital-to-analog converters , 1986 .

[5] G. Temes,et al. A switched-capacitor multiplier/divider with digital and analog outputs , 1984 .

[6] R. Gregorian,et al. Switched-capacitor circuit design , 1983, Proceedings of the IEEE.

[7] R.P. Colbeck. A CMOS low-distortion switched capacitor oscillator with instantaneous start-up , 1984, IEEE Journal of Solid-State Circuits.