Parasitic Extraction of IC Interconnects in Consideration of Optical Distortion by Using Shape Sensitivity Modeling

In the nano-scale IC design, the silicon print image of a layout could be very different from the drawn dimension due to the photolithography effect even with the resolution enhancement technology (RET). To accurately predict the interconnect parasitic resistances and capacitances, the impact of optical distortion needs to be considered. This paper proposes the use of the shape sensitivity analysis to model the optical distortion. The shape sensitivity models are developed with the help of the field solver and can be associated with a pattern match based extraction tool for fast parasitic extraction in consideration of optical effect