Delay line control circuit with delay locked loop(DLL)

PURPOSE: A delay line control circuit of a DLL(Delay Locked Loop) is provided to reduce the jitter by sequentially turning on unit delay cells of the DLL when converting from a wait state to an active state of a DRAM(Dynamic Random Access Memory). CONSTITUTION: A delay line unit(410) receives outputs from front stages to delay them for a predetermined time and includes first to nth unit delay cells(DC1,DC2,...,DCN) outputting the delayed values. The delay line unit(410) receives an inner clock signal as an input of the first unit delay cell(DC1). A control unit(420) generates first to n-th control signals for controlling activation and inactivation of the first to nth unit delay cells(DC1,DC2,-,DCN) in response to a predetermined operation active signal. The first to nth unit delay cells(DC1,DC2,..,DCN) are sequentially activated in response to the operation active signal.