Making fast buffer insertion even faster via approximation techniques

As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing electrical violations. Consequently, buffer insertion is needed on tens of thousands of nets during physical synthesis optimization. Even the fast implementation of van Ginneken's algorithm requires several hours to perform this task. This work seeks to speed up the van Ginneken style algorithms by an order of magnitude while achieving similar results. To this end, we present three approximation techniques in order to speed up the algorithm: (1) aggressive prebuffer slack pruning; (2) squeeze pruning; and (3) library lookup. Experimental results from industrial designs show that using these techniques together yields solutions in 9 to 25 times faster than van Ginneken style algorithms, while only sacrificing less than 3% delay penalty.

[1]  Stephen T. Quay,et al.  Buffer insertion with accurate gate and interconnect delay computation , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[2]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Jiang Hu,et al.  Buffer insertion with adaptive blockage avoidance , 2002, ISPD '02.

[4]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[5]  Jiang Hu,et al.  Buffer insertion with adaptive blockage avoidance , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  J. Lillis,et al.  S-Tree: a technique for buffered routing tree synthesis , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[8]  José Luis Neves,et al.  Buffer library selection , 2000, Proceedings 2000 International Conference on Computer Design.

[9]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[10]  Jason Cong,et al.  Buffered Steiner tree construction with wire sizing for interconnect layout optimization , 1996, ICCAD 1996.

[11]  Noel Menezes,et al.  Repeater scaling and its impact on CAD , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Milos Hrkic,et al.  Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Chung-Kuan Cheng,et al.  New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing , 1996, DAC '96.

[14]  Peter J. Osler Placement driven synthesis case studies on two sets of two chips: hierarchical and flat , 2004, ISPD '04.

[15]  Milos Hrkic,et al.  Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages , 2002, ISPD '02.

[16]  Weiping Shi,et al.  An O(nlogn) time algorithm for optimal buffer insertion , 2003, DAC '03.

[17]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[18]  Weiping Shi,et al.  Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost , 2004 .