Optimized Design of SET D Flip-Flop for Portable Applications

Digital circuits operating in the subthreshold region can have orders of magnitude power advantage over standard circuits for applications requiring ultra low power and medium frequency of operation. This paper presents a modified design of Single Edge Triggered D flip-flop for low power VLSI applications. The proposed modified design consumes less power and area both. The design is tested by applying various substrate bias voltages and the best one is proposed. The proposed design is tested in 65nm and 45nm technologies to prove its technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications.

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