TSV Fault Detection Technique using Eye Pattern Measurements Based on a Non-Contact Probing Method

D-IC is a novel semiconductor packaging technique stacking dies to improve the performance as well as the overall size. TSV is ideal for 3D-IC because it is convenient for stacking and excellent in electrical characteristics. However, due to high-density and micro-size of TSVs, they should be tested with a non-invasive manner. Thus, we introduce a TSV test method on test prober witho ut a direct contact in this paper. A capacitive coupling effect between a probe tip and TSV is used to discriminate small TSV faults like voids and pin-holes. Through EM simulation, we can verify the size of eye-patterns with various frequencies is good for TSV test tools and non-contact test will be promising.

[1]  Krishnendu Chakrabarty,et al.  Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Sherief Reda,et al.  High-throughput TSV testing and characterization for 3D integration using thermal mapping , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Onnik Yaglioglu,et al.  Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integration , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

[4]  Jonghoon J. Kim,et al.  Eye-diagram simulation and analysis of a high-speed TSV-based channel , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[5]  Krishnendu Chakrabarty,et al.  Scan Test of Die Logic in 3-D ICs Using TSV Probing , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Majid Ahmadi,et al.  Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Rashid Rashidzadeh Contactless test access mechanism for TSV based 3D ICs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[8]  Joungho Kim,et al.  Non-contact wafer-level TSV connectivity test methodology using magnetic coupling , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[9]  Erik Jan Marinissen Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Krishnendu Chakrabarty,et al.  Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Krishnendu Chakrabarty,et al.  Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  John P. Hayes,et al.  Contactless testing: Possibility or pipe-dream? , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[13]  William Wu Shen 3DIC system design impact, challenge and solutions , 2014, ISPD '14.

[14]  Hsien-Hsin S. Lee,et al.  A scanisland based design enabling prebond testability in die-stacked microprocessors , 2007, 2007 IEEE International Test Conference.