A power-efficient wide-range signal level-shifter

In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal. The proposed circuit has a small silicon area, low-power consumption and short propagation delay. Post-layout Simulation results for the proposed circuit implemented in a 0.18-μm 1P6M CMOS technology confirm that the power consumption of this circuit is extremely low comparing to other topologies, and is able to operate over a wide range of the input voltages from 50 mV to 1.8 V, and a wide range of frequencies from 100 Hz to 100 MHz. For both a 0.4 V and a 1.8V supply voltages, the proposed circuit has a propagation delay of 10.43 ns and a power consumption of 9.89 nW for a 10-kHz input signal.

[1]  Reza Lotfi,et al.  A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Chi-Ying Tsui,et al.  A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[3]  Wouter A. Serdijn,et al.  An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[4]  Bo Zhai,et al.  A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[5]  Ulrich Rückert,et al.  A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Marco Lanuzza,et al.  Low-Power Level Shifter for Multi-Supply Voltage Designs , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Stuart N. Wooters,et al.  An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[9]  M. Sarrafzadeh,et al.  Simultaneous voltage scaling and gate sizing for low-power design , 2002 .

[10]  Naveen Verma,et al.  Sub-Threshold Design: The Challenges of Minimizing Circuit Energy , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[11]  Gaetano Palumbo,et al.  Evaluation on power reduction applying gated clock approaches , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[12]  Nobutaka Kuroki,et al.  A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs , 2012, IEEE Journal of Solid-State Circuits.