Comparison of Montgomery and Barrett modular multipliers on FPGAs

A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.

[1]  Lejla Batina,et al.  Montgomery in Practice: How to Do It More Efficiently in Hardware , 2002, CT-RSA.

[2]  Holger Orup,et al.  A high-radix hardware algorithm for calculating the exponential M/sup E/ modulo N , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[3]  Shuzo Yajima,et al.  Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem , 1992, IEEE Trans. Computers.

[4]  Allan Tomlinson.  Bit-serial modular multiplier , 1989 .

[5]  MaYutai.  A Simplified Architecture for Modulo (2n + 1) Multiplication , 1998 .

[6]  Mark Shand,et al.  Fast implementations of RSA cryptography , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[7]  C. D. Walter,et al.  Systolic Modular Multiplication , 1993, IEEE Trans. Computers.

[8]  Chin-Chen Chang,et al.  A fast modular multiplication algorithm for calculating the product AB modulo N , 1999, Inf. Process. Lett..

[9]  C. D. Walter,et al.  Montgomery's Multiplication Technique: How to Make It Smaller and Faster , 1999, CHES.

[10]  P. L. Montgomery.  Modular multiplication without trial division , 1985 .

[11]  Colin D. Walter.  Faster Modular Multiplication by Operand Scaling , 1991, CRYPTO.

[12]  Hyunsoo Yoon,et al.  New Modular Multiplication Algorithms for Fast Modular Exponentiation , 1996, EUROCRYPT.

[13]  Arnaud Tisserand,et al.  Comparison of modular multipliers on FPGAs , 2003, SPIE Optics + Photonics.

[14]  Yutai Ma.  A Slimplified Architecture for Modulo (2n + 1) Multiplication , 1998, IEEE Trans. Computers.

[15]  Paul Barrett,et al.  Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor , 1986, CRYPTO.

[16]  Ernest F. Brickell,et al.  A Fast Modular Multiplication Algorithm With Application To Two Key Cryptography , 1982, CRYPTO.

[17]  Reto Zimmermann,et al.  Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[18]  Colin D. Walter.  Still faster modular multiplication , 1995 .

[19]  Xuejia Lai,et al.  On the design and security of block ciphers , 1992 .

[20]  Joos Vandewalle,et al.  A fast and flexible software library for large integer arithmetic , 1994 .