Layout Decomposition for Triple Patterning Lithography

As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140× speed-up even compared with accelerated ILP.

[1]  Patrick Jaenen,et al.  Pitch doubling through dual-patterning lithography challenges in integration and litho budgets , 2007, SPIE Advanced Lithography.

[2]  Zigang Xiao,et al.  A polynomial time triple patterning algorithm for cell based row-structure layout , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Bei Yu,et al.  Implications of triple patterning for 14nm node design and patterning , 2012, Advanced Lithography.

[4]  Puneet Gupta,et al.  A novel methodology for triple/multiple-patterning layout decomposition , 2012, Advanced Lithography.

[5]  Andrew B. Kahng,et al.  Revisiting the layout decomposition problem for double patterning lithography , 2008, Photomask Technology.

[6]  Vincent Wiaux,et al.  Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows , 2009 .

[7]  Evangeline F. Y. Young,et al.  An efficient layout decomposition approach for Triple Patterning Lithography , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  David R. Karger,et al.  Approximate graph coloring by semidefinite programming , 1998, JACM.

[9]  Weitong Chuang,et al.  Delay and area optimization for discrete gate sizes under double-sided timing constraints , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[10]  Martin D. F. Wong,et al.  Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology , 2012, DAC Design Automation Conference 2012.

[11]  Robert E. Tarjan,et al.  A Note on Finding the Bridges of a Graph , 1974, Inf. Process. Lett..

[12]  David Z. Pan,et al.  Methodology for standard cell compliance and detailed placement for triple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Christopher Cork,et al.  Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns , 2008, Photomask Japan.

[14]  Andrew B. Kahng,et al.  New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout , 2001, ASP-DAC '01.

[15]  Sandip Kundu,et al.  Statistical Yield Modeling for Sub-wavelength Lithography , 2008, 2008 IEEE International Test Conference.

[16]  Andrew R. Neureuther,et al.  Post-decomposition assessment of double patterning layouts , 2008, SPIE Advanced Lithography.

[17]  Sungki Park,et al.  Patterning with spacer for expanding the resolution limit of current lithography tool , 2006, SPIE Advanced Lithography.

[18]  Andrew B. Kahng,et al.  Bright-field AAPSM conflict detection and correction , 2005, Design, Automation and Test in Europe.

[19]  Vincent Wiaux,et al.  Double pattern EDA solutions for 32nm HP and beyond , 2007, SPIE Advanced Lithography.

[20]  Andrew B. Kahng,et al.  Fast yield-driven fracture for variable shaped beam mask writing , 2006, Photomask Japan.

[21]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning , 1989, IEEE Trans. Computers.

[22]  David Z. Pan,et al.  A high-performance triple patterning layout decomposer with balanced density , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[23]  C. Mack Fundamental principles of optical lithography , 2007 .

[24]  Andrew B. Kahng,et al.  Improved algorithms for hypergraph bipartitioning , 2000, ASP-DAC '00.

[25]  Yao-Wen Chang,et al.  A novel layout decomposition algorithm for triple patterning lithography , 2012, DAC Design Automation Conference 2012.

[26]  David Z. Pan,et al.  Design for Manufacturing With Emerging Nanolithography , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Hai Zhou,et al.  Layout decomposition with pairwise coloring for multiple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[28]  Yao-Wen Chang,et al.  Native-conflict-aware wire perturbation for double patterning technology , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[29]  Roberto Tamassia,et al.  On Embedding a Graph in the Grid with the Minimum Number of Bends , 1987, SIAM J. Comput..

[30]  Andrew B. Kahng,et al.  Fast and efficient phase conflict detection and correction in standard-cell layouts , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[31]  Anton van Oosten,et al.  Pattern split rules! A feasibility study of rule based pitch decomposition for double patterning , 2007, SPIE Photomask Technology.

[32]  Kun Yuan,et al.  WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[33]  M. Van Hove,et al.  Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm , 2004, SPIE Advanced Lithography.

[34]  Sunyoung Koo,et al.  Issues and challenges of double patterning lithography in DRAM , 2007, SPIE Advanced Lithography.

[35]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[36]  Jae-Seok Yang,et al.  Overlay aware interconnect and timing variation modeling for double patterning technology , 2008, ICCAD 2008.

[37]  Carlo Batini,et al.  Automatic graph drawing and readability of diagrams , 1988, IEEE Trans. Syst. Man Cybern..

[38]  Ping Xu,et al.  Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm , 2011, Advanced Lithography.

[39]  Minsik Cho,et al.  Optimal layout decomposition for double patterning technology , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[40]  David Z. Pan,et al.  Triple patterning lithography (TPL) layout decomposition using end-cutting , 2013, Advanced Lithography.

[41]  C. Mack Fundamental principles of optical lithography : the science of microfabrication , 2007 .

[42]  Qiao Li NP-completeness result for positive line-by-fill SADP process , 2010, Photomask Technology.

[43]  Dwight D. Hill,et al.  Experiments using automatic physical design techniques for optimizing circuit performance , 1990, IEEE International Symposium on Circuits and Systems.

[44]  Ping Xu,et al.  Innovative self-aligned triple patterning for 1x half pitch using single "spacer deposition-spacer etch" step , 2011, Advanced Lithography.

[45]  Bei Yu,et al.  Dealing with IC manufacturability in extreme scaling , 2012, ICCAD '12.

[46]  B. Borchers CSDP, A C library for semidefinite programming , 1999 .

[47]  Kun Yuan,et al.  A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[48]  Yih-Lang Li,et al.  TRIAD: A triple patterning lithography aware detailed router , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[49]  Yue Xu,et al.  A matching based decomposer for double patterning lithography , 2010, ISPD '10.

[50]  Nathan Linial,et al.  On the Hardness of Approximating the Chromatic Number , 2000, Comb..

[51]  Alessandro Vaccaro,et al.  Sub-k1 = 0.25 lithography with double patterning technique for 45-nm technology node flash memory devices at λ = 193nm , 2007, SPIE Advanced Lithography.

[52]  Yici Cai,et al.  SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography , 2013, International Symposium on Quality Electronic Design (ISQED).

[53]  Vincent Wiaux,et al.  Double patterning design split implementation and validation for the 32nm node , 2007, SPIE Advanced Lithography.

[54]  Kun Yuan,et al.  Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[55]  Andrew B. Kahng,et al.  Yield- and cost-driven fracturing for variable shaped-beam mask writing , 2004, SPIE Photomask Technology.

[56]  Chang-Moon Lim,et al.  Positive and negative tone double patterning lithography for 50nm flash memory , 2006, SPIE Advanced Lithography.

[57]  Yue Xu,et al.  GREMA: Graph reduction based efficient mask assignment for double patterning technology , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[58]  Sani R. Nassif,et al.  Simultaneous layout migration and decomposition for double patterning technology , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[59]  Ravi Nair,et al.  Generation of performance constraints for layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[60]  Andrew B. Kahng,et al.  Layout decomposition for double patterning lithography , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[61]  Andrew B. Kahng,et al.  Layout Decomposition Approaches for Double Patterning Lithography , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[62]  Yuelin Du,et al.  Constrained pattern assignment for standard cell based triple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[63]  David S. Johnson,et al.  Some Simplified NP-Complete Graph Problems , 1976, Theor. Comput. Sci..

[64]  David P. Williamson,et al.  The Design of Approximation Algorithms , 2011 .