A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter

A 14-bit 250-MS/s current-steering digital-to-analog converter (DAC) was fabricated in a 0.13 μm CMOS process. In conventional high-speed current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions in the code-dependent switching glitches. In this paper, the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ). Under 250-MS/s sampling rate, the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz. The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

[1]  Brian Miller,et al.  A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz ${\rm f}_{\rm T}$ BiCMOS Process , 2012, IEEE Journal of Solid-State Circuits.

[2]  Gil Engel,et al.  A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  Chi-Hung Lin,et al.  A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[4]  Robert H. M. van Veldhoven,et al.  A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping , 2011, IEEE Journal of Solid-State Circuits.

[5]  R. Adams,et al.  A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[6]  Bang-Sup Song,et al.  A 14 b 100 Msample/s CMOS DAC designed for spectral performance , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[7]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[8]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[9]  Jieh-Tsorng Wu,et al.  A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $70 dB SFDR up to 500 MHz , 2011, IEEE Journal of Solid-State Circuits.

[10]  Michiel Steyaert,et al.  A 10–Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2001 .

[12]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[13]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[14]  Tai-Haur Kuo,et al.  A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection , 2012, IEEE Journal of Solid-State Circuits.

[15]  Hong Zhiliang,et al.  A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS , 2013 .