Modular and efficient architecture for H.263 video codec VLSI

We present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on a modular and unified interface for internal hardware engines, and enables the pipelined operation while keeping enough flexibility to extend the functionality of the VLSI. The developed VLSI supports the H.263 video codec and the low-level protocol processing such as H.223 and H.245, and thus can be used for the complete ITU-T H.324 or 3GPP 3G-324M audiovisual processor with an external audio codec.