An Efficient Path Delay Fault Coverage Estimator

We propose a linear complexity method to estimate robust path delay fault coverage in digital circuits. We adopt a path counting scheme for a true-value simulator that uses flags for each signal line. These ags determine the new path delay faults detected by the simulated vector pair. Experimental results are presented to show the effectiveness of the method in estimating path delay fault coverage.

[1]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[2]  Vishwani D. Agrawal,et al.  Delay fault models and test generation for random logic sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Soumitra Bose,et al.  Path delay fault simulation of sequential circuits , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Michael H. Schulz,et al.  Parallel Pattern Fault Simulation of Path Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  Prathima Agrawal,et al.  Generating tests for delay faults in nonscan circuits , 1993, IEEE Design & Test of Computers.

[6]  Vishwani D. Agrawal,et al.  Logic systems for path delay test generation , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[7]  Irith Pomeranz,et al.  An efficient non-enumerative method to estimate path delay fault coverage , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[9]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.