A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating

Digit serial–serial multipliers are one approach to power-optimize multiplication where operands are fed one digit at a time. This significantly reduces the required chip area and hence reducing power. In this paper, a power-efficient reconfigurable digit serial–serial multiplier is proposed. Power efficiency is achieved using two techniques: reconfiguration and clock gating. Reconfiguration allows the proposed multiplier to perform multiplication of sub-width operands without extending to full width, that is, a multiplier composed of m sub-multipliers each of width n is capable of handling $$mn \times mn$$mn×mn, $$1/2mn \times 1/2mn$$1/2mn×1/2mn, $$1/4mn \times 1/4mn,\ldots , n \times n$$1/4mn×1/4mn,…,n×n multiplications. It also enables the multiplier to perform multiple multiplications concurrently rather than sequentially, that is, the multiplier is capable of handling $$1 \times ( mn \times mn)$$1×(mn×mn), $$2\times (1/2mn \times 1/2), 4\times (1/4mn \times 1/4mn), \ldots , m\times (n\times n)$$2×(1/2mn×1/2),4×(1/4mn×1/4mn),…,m×(n×n) multiplications concurrently. Mathematical operations such as matrix product benefit most from concurrent multiplications. Clock gating is used to reduce power by disabling unused blocks and enabling utilized blocks only when their relevant inputs arrive. Compared with non-reconfigurable no-clock-gating design, simulation results show that the proposed multiplier reduces the power requirement. For $$m=2$$m=2, $$n=32$$n=32, and digit width $$d=4$$d=4 power is reduced by 38 % for $$32\times 32$$32×32 mode and by 49 % for $$2 \times (32 \times 32)$$2×(32×32) mode. Compared with standard parallel multiplier, simulation results also show that the proposed multiplier reduces energy requirement. For $$m=2, n=32$$m=2,n=32, and digit width $$d=32$$d=32, energy is reduced by 46 % for $$32 \times 32$$32×32 mode and by 60 % for $$2 \times (32 \times 32)$$2×(32×32) mode.