Hardening FPGA-based Systems Against SEUs: A New Design Methodology

SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarkscircuits and on a realistic circuit to show the capabilities of the proposed design flow.

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