Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices

High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.

[1]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[2]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[3]  Shahin Nazarian,et al.  Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods , 2006, Proceedings of the IEEE.

[4]  Paolo Emilio Bagnoli,et al.  Validation of the DJOSER analytical thermal simulator for electronic power devices and assembling structures , 2007, Microelectron. J..

[5]  Wei Wu,et al.  Fast thermal simulation for architecture level dynamic thermal management , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[6]  Sheng-Chih Lin,et al.  A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model , 2007, IEEE Transactions on Electron Devices.

[7]  Sung-Mo Kang,et al.  Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages , 2008, ISQED 2008.

[8]  T. Kemper,et al.  Ultrafast Temperature Profile Calculation in Ic Chips , 2006 .

[9]  Kaustav Banerjee,et al.  Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Sung-Mo Kang,et al.  A temperature-aware simulation environment for reliable ULSI chipdesign , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Charlie Chung-Ping Chen,et al.  3-D Thermal-ADI: a linear-time chip level transient thermal simulator , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Ismo V. Lindell.  Image theory for electromagnetic sources in chiral medium above the soft and hard boundary , 2001 .

[13]  Xi Wang,et al.  Power Trace: An Efficient Method for Extracting the Power Dissipation Profile in an IC Chip From Its Temperature Map , 2009, IEEE Transactions on Components and Packaging Technologies.

[14]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Gordon E. Moore,et al.  Progress in digital integrated electronics , 1975 .

[16]  Je-Hyoung Park,et al.  Method of images for the fast calculation of temperature distributions in packaged VLSI chips , 2007, 2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC).

[17]  X. Perpina,et al.  Reduced-Order Thermal Behavioral Model Based on Diffusive Representation , 2009, IEEE Transactions on Power Electronics.

[18]  A. Shakouri,et al.  Fast thermal simulations of vertically integrated circuits (3D ICs) including thermal vias , 2012, 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

[19]  Paul D. Franzon,et al.  Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Sung-Mo Kang,et al.  Fast Computation of Temperature Profiles of VLSI ICs with High Spatial Resolution , 2008, 2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[21]  S. Kang,et al.  FAST THERMAL ANALYSIS OF VERTICALLY INTEGRATED CIRCUITS (3-D ICS) USING POWER BLURRING METHOD , 2009 .

[22]  Jose Renau,et al.  Thermal-aware sampling in architectural simulation , 2012, ISLPED '12.

[23]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[24]  Sung-Mo Kang,et al.  Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Ali Shakouri,et al.  Thermal characterization of high power transistor arrays , 2009, 2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[26]  Jose Renau,et al.  Fast thermal simulators for architecture level integrated circuit design , 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[27]  Kevin Skadron,et al.  Temperature-Aware Computer Systems: Opportunities and Challenges , 2003, IEEE Micro.

[28]  A. Shakouri,et al.  Enabling power density and thermal-aware floorplanning , 2012, 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[29]  Li Shang,et al.  ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[31]  Brad Burgess,et al.  Bobcat: AMD's Low-Power x86 Processor , 2011, IEEE Micro.

[32]  K. Banerjee,et al.  An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[33]  Jose Renau,et al.  Characterizing processor thermal behavior , 2010, ASPLOS XV.

[34]  Israel Koren,et al.  TILTS: A Fast Architectural-Level Transient Thermal Simulation Method , 2007, J. Low Power Electron..

[35]  Paolo Maffezzoni,et al.  An Arnoldi based thermal network reduction method for electro-thermal analysis , 2003 .

[36]  Pinaki Mazumder,et al.  Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[37]  Sachin S. Sapatnekar,et al.  A high efficiency full-chip thermal simulation algorithm , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..