This paper presents a high-speed LVDS I/O interface for mobile DRAMs. A data rate of 6Gbps/pin and a transmit-jitter of 57.31ps pk-pk were demonstrated, in which an 800MHz clock and a 200mV swing were used. The power consumption by I/O circuit is 6.2mW/pin when a 10pf load is connected to the I/O, and output supply voltage is 1.2V. The proposed mobile DRAM has 6 data pins and 4 address/command pins for a multi-chip package (MCP). The transmitter uses a feed-back LVDS output driver and a common-mode feed-back controller achieving the reduction of driver currents and the constant common-mode as half voltage level. To achieve a low-transmit jitter, we use a driver with a double step pre-emphasis. The receiver employs a shared preamplifier scheme, which ensures transmit power reduction. The proposed DRAM with LVDS I/O was fabricated using an 80-nm DRAM process. It exhibits 161.1mV times 150ps rms eye-windows on the given channel
[1]
J. Silva-Martinez,et al.
Low-voltage low-power LVDS drivers
,
2005,
IEEE Journal of Solid-State Circuits.
[2]
Suki Kim,et al.
A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory
,
2004,
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[3]
A. Boni,et al.
LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS
,
2001
.
[4]
Jung-Hwan Choi,et al.
A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling
,
2005,
IEEE Journal of Solid-State Circuits.
[5]
Pradip Mandal,et al.
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation
,
2004,
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).